MCASP1 interface of the processor is connected to the audio interface of the codec. The LLD expects single interrupt for both Ports. So, the low priority queues are Queue 2 and Queue 4 for Port 1 and Port 2 respectively. Technical Reference Manual for an SoC. Another important difference which is obvious from the name is that an EMAC does not forward a packet from one port to another like a Switch. The interrupt configuration is explained in detail in the interrupts section.
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Typically you would set this to 00 to save power during idle. Termination is typically not needed for writes, so this value should be set to 0. Each DDR type has a different procedure for determining these values. Please refer to the section below for your DDR type. Refer to the TRM for an explanation of these registers.
Note: due to a bug in the device, these registers are not readable. They are write only registers. For CMDx, x is 0,1,2 as described above. For DATAx, x is 0 or 1 as described above. In all cases, program the same value for each iteration of the macro. Ensure that you input the trace length from AMx to each memory. These lengths should be close to equal if correct design guidelines were met.
After inputting the correct information, the values for the registers will be automatically calculated in the spreadsheet. Here is a summary of their configuration. Refer to the TRM to determine which group of signals are affected by each register. For programming purposes, each of these registers should be set to the same value. Ensure that you enter the correct values for the speed grade of your device. The tCK value should represent the speed at which you will be running the device not necessarily the minimum value in the datasheet.
The register values for the AMx AC timing registers will be calculated based on these inputs. Ultimately, the optimal values should work. Note that this value is typcially in the us range. Some datasheets may refer to a "Refresh Interval time" in the millisecond range 64ms, for example , however, this value needs to be divided by the number of refresh cycles needed typically This field is not byte writable, i.
Here are some examples: For MHz memory system with 7. There are 3 levels of power management that you can set with this register: clock stop, self-refresh, and power-down. The register also gives you the flexibility to set timers that monitor EMIF idle time.
When they expire, then the EMIF will put the external memory in the mode that is designated. Some power modes are only supported by certain memories. Number of clock cycles to wait after EMIF is idle before going into power saving mode.
This is the number of clock cycles to wait after EMIF is idle before going into self-refresh mode. This is the number of clock cycles to wait after EMIF is idle before going into clock stop mode. Shadow Registers The AMx devices support smart idle mode for power conservation.
Upon returning from smart idle mode, the shadow registers are loaded into the EMIF registers. DDR memories typically have configurable On Die Termination internally which helps improve signal integrity.
These bits determine the ODT value applied on the memory side. Typically ODT is turned off during reads and self refresh states, and turned on during writes. This allows the memory to apply a different ODT value from the nominal value described above. This ODT value is only applied by the memory during write cycles. When to use nominal vs.
Another scenario might be if you require a different ODT termination value for writes vs. For DDR2.
AM335X TRM PDF
Faugami Serial number of the board. Figure 3 Reset button and buffer with APX supervisor circuit The connections are made as shown in Figure 3 Schematic updates are shown using dotted lines. Forwarding Rules specify how packets are forwarded between ports and from the port to the Host. The convention used here is two physical ports and one host port.
AM335x U-Boot User's Guide
Typically you would set this to 00 to save power during idle. Termination is typically not needed for writes, so this value should be set to 0. Each DDR type has a different procedure for determining these values. Please refer to the section below for your DDR type.
AM335x EMIF Configuration tips