IMPLEMENTATION OF CONVOLUTIONAL ENCODER AND VITERBI DECODER USING VHDL PDF

Gabar The ACS block generates the survivor path information using the vitedbi branch metric and current state metric. The survival selection is implemented by 8 bit subtraction, the path metric of the survival is stored in 8 bit register inside ACS usint. The input-output pin assignment is shown in the following tables. Convolution coding scheme can be applied to both continuously running data stream as well as to blocks of data, whereas block codes are suited only for the latter. Entity shiftadd functions as the shift registers and the modulo-2 chdl and entity mux21 is the multiplexer of the encoder system.

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The convolutional encoder with Viterbi decoder is more powerful structure for forward error correction technique. The maximum likelihood is the basic principle of Viterbi algorithm. The proposed design of encoder and viterbi decoder has been realized using matlab. Introduction Convolution coding is used in communication such as satellite and space communication to improve communication efficiency.

The convolution code has enriched with the gift of a linear code with quality properties that it can operate on serial data as well as block codes. The convolution encoder with viterbi decoder is a forward error correction method is mostly suited to a channel in which the transmitted signal is corrupted because of additive white Gaussian noise.

The Viterbi decoding was developed by Andrew J. Viterbi who is a founder of Qualcomm Inc. Since then, other researchers have expanded on his work by finding good convolution codes, exploring the performance limits of the technique, and varying decoder design parameters to optimize the implementation of the technique in hardware and software [3]. The viterbi algorithm has now used in large number of applications.

This algorithm works with trellis structure, which gives trace back for decoding the received information [3]. The fixed decoding time is the great advantage of the viterbi decoder because of this it is well suited to hardware decoder implementation. The convolutional coding with Viterbi decoding has been the predominant FEC technique used in space communication, particularly in geostationary satellite communication networks, such as VSAT very small aperture terminal networks [3].

Convolution encoder with viterbi decoder is a powerful method for forward error correction technique. The principle of viterbi algorithm is maximum likelihood decoding. Input data stream is fed to the convolution encoder, which produces encoded output stream according to designed encoder specification. The encoded data steam travels through channel having presence of noise, produces the new encoded stream with noise.

Finally, this noisy data is given to the viterbi decoder that produces the corrected data which is applied to the encoder as input [2]. The motivation of this paper is to understand basic concept of both convolution encoder and viterbi decoder using matlab tool with both script language and simulink having constraint length 3. Block diagram of Encoder and Decoder II.

Convolutional Encoder Convolution code are commonly specified by three parameters n, k, m , where n is number of output bits, k is number of input bits and m is number of memory registers.

The convolutional encoder is easy to draw from its parameters shown in Figure2. Pednekar et al. The selection of which bits are to be added to produce the output bits is called generator polynomial for output bit. In this paper, C1 and C2 represent generator polynomials as output bits of two modulo-2 adders. The generator polynomials C1 and C2 are of , i.

The polynomials give the code its unique protection quality [4]. The constraints length of code is three. If this stream is not maintained then decoder will not give error corrected output hence we have to take care of bit synchronization. In this paper, we are considering that decoder is receiving synchronized input bits. Block diagram of convolutional encoder Graphically, there are three ways to understand operation of the encoder.

These are state diagram, tree diagram and trellis diagram [4]. State Diagram A state diagram for encoder, Figure3, is of four states corresponding to the binary contents of the memory registers FF1 and FF2 of the encoder. The lines joining states indicates transition due to input of single information bit. Tree Diagram Figure4 shows another method of understanding operation of convolution encoder. It is somewhat better than a state diagram but still not preferred approach for representing convolutional code [4].

The bits outside the parenthesis are output bits C1C2 and the bits inside the parenthesis are represents next state i. Trellis Diagram Trellis diagrams are little complex than state and tree diagram still they are more preferable for higher constraint length [4]. State diagram of 2, 1, 3 code Figure4. Tree diagram of 2, 1, 3 code III. Viterbi decoder There are two basic categories to decoding convolutional codes.

These are sequential decoding and maximum likelihood decoding based on Fano algorithm and Viterbi algorithm respectively [4]. Viterbi decoding was first shown to be an efficient and practical decoding technique for short constraint length codes by Heller.

Forney and Omura demonstrated that the algorithm was in fact maximum likelihood [1]. It uses trellis diagram to compute branch metric and path metric from received signal to possible transmitted signal. Figure5 gives idea about trellis diagram. It has discrete time on horizontal x-axis while possible states on vertical y-axis. Trace-back length T is five to six times of constraint length. As per algorithm decoding started at state 0. When a sequence of data is received from channel, it is desirable to estimate the original sequence that has been sent.

And this process can be done with the help of trellis. The bubble shows the states at each time interval. The solid line connecting dots in the diagram represents the state transitions when input bit is zero and the dotted line represents state transitions when input bit is one.

The bits which are corresponding with solid and dotted lines represent encoder polynomial generator outputs. Trellis diagram for hard decision viterbi decoder A. Decoding started with hamming distance calculation shown in Figure2 as block HD. General structure of Viterbi Decoder Figure7. Branch and Path metric calculation at a node There are two types of viterbi decoder, hard decision and soft decision.

A hard decision decoder uses 1- bit quantization, and uses hamming distance metric to find the distance between expected signal and actual received signal. Other hand soft decision decoder uses multi bit quantization and uses Euclidean distance as metric.

The soft decision decoding is expensive and requires more memory than hard decision. This paper focuses on hard decision decoder.

Hamming Distance There are four possible hamming distances. These are depends on how many polynomial generators used during encoder design. As shown in Figure2, encoder has two generators polynomial so there are four possible cases to calculate hamming distances; these are 00, 01, 10, and Hence, zero, one and two, these are possible hamming distances.

At each node of state there are two branch metrics. In viterbi decoder, the path metric is calculated for all state nodes as per constraints length which is further helpful during trace-back for that it is stored in path memory. If this path history memory is fixed amount, then the decoder can output the oldest bit on an arbitrary path each time it steps one level deeper into the trellis [5].

Survivor Memory Unit The survivor memory stores the state having minimum path metric. And finally these states are used to get decoded bits, i. The path comparisons made for paths entering each state require the calculation of the likelihood of each path involved for the particular received information [5].

Proposed design simulation in Matlab Viterbi decoder presented here is totally based on flow graph shown in Figure8. Operation can be discussed as shown in the flow graph; taking constraints length L is equal to 3, in case of Figure2 as an example.

Then as discussed in section III-C, hamming distance has been calculated. The branch metric for the two paths entering at state 00 are calculated by adding the previous path metric and hamming distance of the previous states 00 and Here, the first part of Add-Compare-Select i.

Add has done. Same addition is done using adders at each state node. Compare-Select is the next part in which comparison between branch metrics computed. The minimum of branch metric is stored as new path metric of that state node.

This Add-Compare-Select operation performed for the all state nodes. Once, all state are available for trace-back length the final step of trace-back has been performed to get corrected decoded output. Finding state is depends on the previous state. Also if the minimum state is 2 or 4, then state selection at t-1 will between 3 and 4. Now here, is all state available to find decoded bits Figure Yes Is trellis end? Result analysis In Matlab The results for proposed viterbi decoder with corrected outputs with intermediate steps are discussed in this section which is very useful to understand the design.

The PN sequence generator of polynomial [19 18 17 14 0] generate random binary signal. The signals generated at each block shown in figure Noise introduced in the channel is of 7dB. Path metric calculation for each state and each time instance has done with module shown in figure 11 with add-compare-select unit. Unit delay is to get previous path metric for further calculation of path metric. Proposed design of system for convolution encoder with Figure Delayed PN sequence generator output, modulated viterbi decoder.

Branch metric and path metric unit including Add- Figure Path metric outputs for all four state as the outputs of Figure Add-Compare-Select Unit.

This requirement is fulfillment and gives the following delayed output.

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