Wrap-Around Use caution with indexed zero page operations as they are subject to wrap-around. This characteristic can be used to advantage but make sure your code is well commented. In cases where you are writing code that will be relocated you must consider wrap-around when assigning dummy values for addresses that will be adjusted. The use of zero or zero page values will result in assembled code with zero page opcodes when you wanted absolute codes.
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EA Instruction timing The time required for instruction to execute is regular and predictable. The primary rule is this: Each byte read from or written to memory requires one clock cycle. All single-byte instructions waste a cycle reading and ignoring the byte that comes immediately after the instruction this means no instruction can take less than two cycles. Zero page,X, zero page,Y, and zero page,X addressing modes spend an extra cycle reading the unindexed zero page address.
Absolute,X, absolute,Y, and zero page ,Y addressing modes need an extra cycle if the indexing crosses a page boundary, or if the instruction writes to memory. The conditional branch instructions require an extra cycle if the branch actually happens, and a second extra cycle if the branch happens and crosses a page boundary.
RTS needs an extra cycle in addition to the single-byte penalty and the pull-from-stack penalty to increment the return address. JSR spends an extra cycle juggling the return address internally. The question often arises, "What do all those other leftover bytes do if you try to execute them as instructions? Those looking for a precise listing of "undocumented" instruction behaviors will have to look elsewhere, and should beware that the behaviors described on other web pages may be specific to s made by a particular often unspecified manufacturer.
However, there are some facts that seem to be common across all s. In some cases the 01 and 10 instructions are incompatible. So which register actually gets written to memory?
Usually some mixture of the two, in a manner that varies depending on who made the , when it was made, the phase of the moon, and other unpredictable variables. The behavior of the 11 instructions is especially problematic in those cases where the adjacent 01 or 10 instruction is also undocumented.
Xxxx instructions are also problematic--some of these seem to mix not only the adjacent 01 and 10 instructions, but also the immediate mode of the corresponding 10 instruction. Most of the missing 00, 01, and 10 instructions seem to behave like NOPs, but using the addressing mode indicated by the bbb bits. Instructions of the form xxxx usually lock up the processor, so that a reset is required to recover.
Some instructions landed in logical places, but others had to be assigned wherever there was room, whether it made sense or not.
6502 Unsupported Opcodes
In decimal mode, addition is carried out on the assumption that the values involved are packed BCD Binary Coded Decimal. There is no way to add without carry. The S and V flags are set to match bits 7 and 6 respectively in the value stored at the tested address. Branch Instructions Affect Flags: none All branches are relative mode and have a length of two bytes. Syntax is "Bxx Displacement" or better "Bxx Label".
Jump to: navigation , search The is famous for doing interesting and sometimes useful things when the program includes invalid or unspecified opcodes. For a list of all opcodes and some explanation of what they do, see all Opcodes. The visual simulator can help when investigating what these opcodes do, and why - see below for a few cases and pointers for exploration. For some of these opcodes, the chip does something logically predictable and our model has the same behaviour. But there may be opcodes which are not logically predictable, because they cause marginal voltages on the chip as different drivers fight one another, or a node which is undriven is sampled at a later time. A simulator could let you know that something is amiss But note that the underlying circuit data which we now have includes transistor strengths and an approximation of capacitative load: it could easily be extended for resistance and more accurate capacitance. So a more refined lower level simulation might shed more light on these undocumented opcodes.
6502 Instruction Set
The address of the branch destination LABEL in the syntax example above must be within to bytes inclusive of the address of the next instruction or data after the BRA, that is, 2 bytes plus the address of the BRA opcode. The branch is to a different page when the next instruction after the BRA is on a different page than the branch destination. Note that this is the same cycle count as the other branch instructions. Since the other branches are conditional, they will take 2 cycles if the branch is not taken i. PHX 5A 1 3 imp Note that the cycle counts are the same as STA. First, the term reset is used to refer to the clearing of a bit, whereas the term clear had been used consistently before, such as CLC which stands for CLear Carry.