The split-gate cell design and thick oxide tunneling injector attain better reliability and manufacturability compared with alternate approaches. To pro- tect against inadvertent write, they have on-chip hardware and software data protection schemes. Designed, manu- factured, and tested for a wide spectrum of applications, these devices are offered with a guaranteed endurance of 10, cycles. Data retention is rated at greater than years. For all system applications, they signifi- cantly improve performance and reliability, while lowering power consumption.
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Single Voltage Read and Write Operations — 3. A typical? Latched Address and Data? The split-gate cell design and thick oxide tunneling injector attain better reliability and manufacturability compared with alternate approaches. To protect against inadvertent write, they have on-chip hardware and software data protection schemes.
Designed, manufactured, and tested for a wide spectrum of applications, these devices are offered with a guaranteed endurance of 10, cycles. Data retention is rated at greater than years. For all system applications, they significantly improve performance and reliability, while lowering power consumption. They inherently use less energy during Erase and Program than alternative flash technologies.
When programming a flash device, the total energy consumed is a function of the applied voltage, current, and time of application. Since for any given voltage range, the SuperFlash technology uses less current to program and has a shorter erase time, the total energy consumed during any Erase or Program operation is less than alternative flash technologies.
These devices also improve flexibility while lowering the cost for program, data, and configuration storage applications. See Figures 1 and 2 for pinouts. These specifications are subject to change without notice. Commands are written to the device using standard microprocessor write sequences. A command is written by asserting WE low while keeping CE low. The address bus is latched on the falling edge of WE or CE , whichever occurs last.
The data bus is latched on the rising edge of WE or CE , whichever occurs first. CE is used for device selection. When CE is high, the chip is deselected and only standby power is consumed. OE is the output control and is used to gate data from the output pins.
The data bus is in high impedance state when either CE or OE is high. Refer to the Read cycle timing diagram for further details Figure 3. Erase operation is initiated by executing a six-byte command sequence with Sector-Erase command 30H and sector address SA in the last bus cycle.
The Block-Erase operation is initiated by executing a six-byte command sequence with Block-Erase command 50H and block address BA in the last bus cycle. The sector or block address is latched on the falling edge of the sixth WE pulse, while the command 30H or 50H is latched on the rising edge of the sixth WE pulse. The internal Erase operation begins after the sixth WE pulse. See Figures 9 and 10 for timing waveforms. Any commands issued during the Sectoror Block-Erase operation are ignored.
This is useful when the entire device must be quickly erased. The Chip-Erase operation is initiated by executing a sixbyte command sequence with Chip-Erase command 10H at address H in the last byte sequence. See Table 4 for the command sequence, Figure 8 for timing diagram, and Figure 19 for the flowchart. Any commands issued during the Chip-Erase operation are ignored.
Before programming, one must ensure that the sector, in which the word which is being programmed exists, is fully erased. The Program operation consists of three steps. The first step is the three-byte load sequence for Software Data Protection. The second step is to load word address and word data. During the Word-Program operation, the addresses are latched on the falling edge of either CE or WE , whichever occurs last. The data is latched on the rising edge of either CE or WE , whichever occurs first.
The third step is the internal Program operation which is initiated after the rising edge of the fourth WE or CE , whichever occurs first. The Program operation, once initiated, will be completed within 20? During the internal Program operation, the host is free to perform additional tasks.
Any commands issued during the internal Program operation are ignored. The End-of-Write detection mode is enabled after the rising edge of WE , which initiates the internal Program or Erase operation. The actual completion of the nonvolatile write is asynchronous with the system; therefore, either a Data Polling or Toggle Bit read may be simultaneous with the completion of the write cycle.
If this occurs, the system may possibly get an erroneous result, i. In order to prevent spurious rejection, if an erroneous result occurs, the software routine should include a loop to read the accessed location an additional two 2 times. If both reads are valid, then the device has completed the write cycle, otherwise the rejection is valid.
The sector architecture is based on uniform sector size of 2 KWord. The Block-Erase mode is based on uniform block size of 32 KWord. The Sector? Once the Program operation is completed, DQ7 will produce true data. The device is then ready for the next operation. See Figure 6 for Data Polling timing diagram and Figure 17 for a flowchart. Any Program operation requires the inclusion of the three-byte sequence. The three-byte load sequence is used to initiate the Program operation, providing optimal protection from inadvertent Write operations, e.
Any Erase operation requires the inclusion of six-byte sequence. This group of devices are shipped with the Software Data Protection permanently enabled. See Table 4 for the specific software command codes. When the internal Program or Erase operation is completed, the DQ6 bit will stop toggling.
See Figure 7 for Toggle Bit timing diagram and Figure 17 for a flowchart. This prevents inadvertent writes during power-up or power-down. This mode may be accessed by software operations. Users may use the Software Product Identification operation to identify the part i. Exit is accomplished by issuing the Software ID Exit command sequence, which returns the device to the Read mode. This command may also be used to reset the device to the Read mode after any inadvertent transient condition that apparently causes the device to behave abnormally, e.
See Table 4 for software command codes, Figure 13 for timing waveform and Figure 18 for a flowchart. Data 00BFH H? To output data during Read cycles and receive input data during Write cycles.
Data is internally latched during a Write cycle. The outputs are in tri-state when OE or CE is high. To activate the device when CE is low. To gate the data output buffers. To control the Write operations. To provide power supply voltage: 3. Refer to CFI publication for more details. This is a stress rating only and functional operation of the device at these conditions or conditions greater than those defined in the operational sections of this data sheet is not implied.
Exposure to absolute maximum stress rating conditions may affect device reliability. Temperature Under Bias. Voltage on Any Pin to Ground Potential. Outputs shorted for no more than one second. No more than one output shorted at a time. This parameter is measured only for initial qualification and after a design or process change that could affect this parameter.
The WE and CE signals are interchageable as long as minimum timings are met. Measurement reference points for inputs and outputs are VIT 0. Yes No Does DQ6 match? Consult your SST sales representative to confirm availability of valid combinations and to determine availability of new combinations.
Scale is mm. Coplanarity: 0. Maximum allowable mold flash is 0. The actual shape of the corners may be slightly different than as portrayed in the drawing. Sunnyvale, CA ? Telephone ? Fax www.