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Cascadable for up to eight devices? Hardware write protect for entire array? Schmitt trigger inputs for noise suppression? It has been developed for advanced, low power applications such as personal communications or data acquisition. This device also has a page-write capability of up to 64 bytes of data. This device is capable of both random and sequential reads up to the K boundary.
Functional address lines allow up to eight devices on the same bus, for up to 2 Mbit address space. This is a stress rating only and functional operation of the device at those or any other conditions above those indicated in the operational listings of this speci?
Exposure to maximum rating conditions for extended periods may affect device reliability. As a transmitter, the device must provide an internal minimum delay time to bridge the unde? This eliminates the need for a TI speci? This parameter is not tested but guaranteed by characterization. For endurance estimates in a speci? The levels on these inputs are compared with the corresponding bits in the slave address.
The chip is selected if the compare is true. Up to eight devices may be connected to the same bus by using different chip select bit combinations. If left unconnected, these inputs will be pulled down internally to VSS. An internal pull-down on this pin will keep the device in the unprotected state if left?
If tied to VSS or left? Read operations are not affected. A device that sends data onto the bus is de? Both master and slave can operate as a transmitter or receiver, but the master device determines which mode is activated. DSC-page 4 4. Data transfer may be initiated only when the bus is not busy. During data transfer, the data line must remain stable whenever the clock line is HIGH.
Accordingly, the following bus conditions have been de? All operations must end with a STOP condition. The data on the line must be changed during the LOW period of the clock signal. There is one bit of data per clock pulse. The master device must generate an extra clock pulse which is associated with this acknowledge bit.
Note: The 24xx does not generate any acknowledge bits if an internal programming cycle is in progress. Of course, setup and hold times must be taken into account. During reads, a master must signal an end of data to the slave by NOT generating an acknowledge bit on the last byte that has been clocked out of the slave.
Data from transmitter Receiver must release the SDA line at this point so the Transmitter can continue sending data. The control byte consists of a 4-bit control code; for the 24xx this is set as binary for read and write operations.
The next three bits of the control byte are the chip select bits A2, A1, A0. The chip select bits allow the use of up to eight 24xx devices on the same bus and are used to select which device is accessed. The chip select bits in the control byte must correspond to the logic levels on the corresponding A2, A1, and A0 pins for the device to respond.
These bits are in effect the three most signi? The last bit of the control byte de? When set to a one a read operation is selected, and when set to a zero a write operation is selected. The next two bytes received de?
The upper address bits are transferred? Following the start condition, the 24xx monitors the SDA bus checking the control byte being transmitted. Upon receiving a code and appropriate device select bits, the slave device outputs an acknowledge signal on the SDA line. In this case, software can use A0 of the control byte as address bit A15; A1, as address bit A16; and A2, as address bit A It is not possible to read or write across device boundaries.
A 0 DSC-page 6? This indicates to the addressed slave receiver that the address high byte will follow after it has generated an acknowledge bit during the ninth clock cycle. Therefore the next byte transmitted by the master is the high-order byte of the word address and will be written into the address pointer of the 24xx The next byte is the least significant address byte. After receiving another acknowledge signal from the 24xx, the master device will transmit the data word to be written into the addressed memory location.
The 24xx acknowledges again and the master generates a stop condition. This initiates the internal write cycle, and, during this time, the 24xx will not generate acknowledge signals Figure If an attempt is made to write to the array with the WP pin held high, the device will acknowledge the command but no write cycle will occur, no data will be written, and the device will immediately accept a new command. After a byte write command, the internal address counter will point to the address location following the one that was just written.
But instead of generating a stop condition, the master transmits up to 63 additional bytes, which are temporarily stored in the on-chip page buffer and will be written into memory after the master has transmitted a stop condition. After receipt of each word, the six lower address pointer bits are internally incremented by one. If the master should transmit more than 64 bytes prior to generating the stop condition, the address counter will roll over and the previously received data will be overwritten.
As with the byte write operation, once the stop condition is received, an internal write cycle will begin Figure If an attempt is made to write to the array with the WP pin held high, the device will acknowledge the command but no write cycle will occur, no data will be written, and the device will immediately accept a new command subject to TBUF.
Once the stop condition for a write command has been issued from the master, the device initiates the internally timed write cycle. ACK polling can be initiated immediately.
If the device is still busy with the write cycle, then no ACK will be returned. If no ACK is returned, then the start bit and control byte must be resent. If the cycle is complete, then the device will return the ACK, and the master can then proceed with the next read or write command.
See Figure for? There are three basic types of read operations: current address read, random read, and sequential read. The master will not acknowledge the transfer but does generate a stop condition and the 24xx discontinues transmission Figure To perform this type of read operation,?
After the word address is sent, the master generates a start condition following the acknowledge. This terminates the write operation, but not before the internal address pointer is set. The 24xx will then issue an acknowledge and transmit the 8-bit data word. The master will not acknowledge the transfer but does generate a stop condition which causes the 24xx to discontinue transmission Figure After a random read command, the internal address counter will point to the address location following the one that was just read.
This acknowledge directs the 24xx to transmit the next sequentially addressed 8-bit word Figure Following the? To provide sequential reads, the 24xx contains an internal address pointer which is incremented by one at the completion of each operation. This address pointer allows the entire memory contents to be serially read during one operation. The internal address pointer will automatically roll over from address 7FFF to address if the master acknowledges the byte received from the array address 7FFF.
To determine if an errata sheet exists for a particular device, please contact one of the following: 1. Your local Microchip sales of? FAX: Please specify which device, revision of silicon and Data Sheet include Literature you are using. India Liaison Of? Information contained in this publication regarding device applications and the like is intended for suggestion only and may be superseded by updates.
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24LC256-I/SN Microchip Technology Inc., 24LC256-I/SN Datasheet
24LC256 MICROCHIP PDF